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| LPC1850/30/20/10 32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller Rev. 1 -- 3 January 2011 Objective data sheet 1. General description The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM, a quad SPI Flash Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. 2. Features and benefits Processor core ARM Cortex-M3 processor, running at frequencies of up to 150 MHz. ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input. JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points. ETM and ETB support. System tick timer. On-chip memory 136 kB SRAM for code and data use. Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be powered down individually. 32 kB ROM containing boot code and on-chip software drivers. 32-bit One-Time Programmable (OTP) memory for general-purpose customer use. Clock generation unit Crystal oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz internal RC oscillator trimmed to 1 % accuracy. Ultra-low power RTC crystal oscillator. NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Two PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. Second PLL can be used for USB. Clock output. Serial interfaces: Quad SPI Flash Interface (SPIFI) with four lanes and data rates of up to 40 MB per second total. 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip PHY. One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY. Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support synchronous mode and a smart card interface conforming to ISO7816 specification. One C_CAN 2.0B controller with one channel. Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support. One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s. One standard I2C-bus interface with monitor mode and standard I/O pins. One I2S interface with DMA support and with one input and one output. Digital peripherals: External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices. LCD controller with DMA support and a programmable display resolution of up to 1024H x 768V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping. SD/MMC card interface. Eight-channel General-Purpose DMA (GPDMA) controller can access all memories on the AHB and all DMA-capable AHB slaves. Up to 80 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors and open-drain modes. GPIO registers are located on the AHB for fast access. GPIO ports have DMA support. State Configurable Timer (SCT) subsystem on AHB. Four general-purpose timer/counters with capture and match capabilities. One motor control PWM for three-phase motor control. One Quadrature Encoder Interface (QEI). Repetitive Interrupt timer (RI timer). Windowed watchdog timer. Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers. Alarm timer; can be battery powered. Analog peripherals: One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 2 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Security: AES decryption engine programmable through an on-chip API. Two 128-bit secure OTP memories for AES key storage and customer use. Unique ID for each device. Power: Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain. RTC power domain can be powered separately by a 3 V battery supply. Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Overdrive mode to increase CPU and bus clock frequency. Processor wake-up from Sleep mode via wake-up interrupts from various peripherals. Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain. Brownout detect with four separate thresholds for interrupt and forced reset. Power-On Reset (POR). Available as 208-pin and 144-pin LQFP packages and as 100-pin, 180-pin, and 256-pin LBGA packages. 3. Applications Industrial Consumer White goods RFID readers e-Metering 4. Ordering information Table 1. Ordering information Package Name LPC1850FET256 LPC1850 LPC1850 LPC1830FET256 LPC1830 LPC1830 LPC1820 LPC1820FET100 LPC1810 LPC1810FET100 LBGA256 LQFP208 BGA180 LBGA256 LQFP208 BGA180 LQFP144 BGA100 LQFP144 BGA100 Description plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 3 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 4.1 Ordering options Table 2. Ordering options SRAM 200 kB 200 kB 200 kB 200 kB 200 kB 200 kB 168 kB 168 kB 136 kB 136 kB LCD yes yes yes no no no no no no no Ethernet yes yes yes yes yes yes no no no no USB0 (Host, Device, OTG) yes yes yes yes yes yes yes yes no no USB1 (Host, Device) yes yes yes yes yes yes no no no no Package LBGA256 LQFP208 BGA180 LBGA256 BGA180 LQFP208 BGA100 LQFP144 BGA100 LQFP144 Type number LPC1850 LPC1850 LPC1850 LPC1830 LPC1830 LPC1830 LPC1820 LPC1820 LPC1810 LPC1810 LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 4 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 5. Block diagram SWD/TRACE PORT/JTAG LPC1850/30/20/10 HIGH-SPEED PHY TEST/DEBUG INTERFACE GPDMA ARM CORTEX-M3 I-code bus BRIDGE 0 WWDT USART0 UART1 SSP0 TIMER0 TIMER1 SCU D-code bus system bus ETHERNET(1) 10/100 MAC IEEE 1588 HIGHSPEED USB0(1) HOST/ DEVICE/ OTG USB1(1) HOST/ DEVICE LCD(1) SD/ MMC(1) masters slaves AHB MULTILAYER MATRIX slaves SPIFI EMC 32 kB ROM BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE BRIDGE MOTOR CONTROL PWM I2C0 I2S0 RI TIMER USART2 USART3 TIMER2 TIMER3 SSP1 I2C1 10-bit DAC C_CAN 10-bit ADC0 10-bit ADC1 CGU CCU1 CCU2 RGU ALARM TIMER BACKUP REGISTERS POWER MODE CONTROL CONFIGURATION REGISTERS EVENT ROUTER OTP MEMORY 64/96 kB LOCAL SRAM 40 kB LOCAL SRAM 16/32 kB AHB SRAM 16 kB + 16 kB AHB SRAM(1) AES HS GPIO SCT QEI RTC RTC OSC 12 MHz IRC = connected to GPDMA RTC POWER DOMAIN 002aaf218 (1) Not available on all parts (see Table 2). Fig 1. LPC1850/30/20/10 block diagram LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 5 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 6. Pinning information 6.1 Pinning LPC1850/30FET256 2 1 A B C D E F G H J K L M N P R T 002aaf230 ball A1 index area 4 3 5 6 7 8 9 10 11 12 13 14 15 16 Transparent top view Fig 2. Pin configuration LBGA256 package 6.2 Pin description On the LPC1850/30/20/10, digital pins are grouped into 16 ports, named P0 to P9 and PA to PF, with up to 20 pins used per port. Each digital pin may support up to four different digital functions, including General Purpose I/O (GPIO), selectable through the SYSCON registers. Note that the pin name is not indicative of the GPIO port assigned to it. Analog functions and power pins are pinned out separately and do not share pins with digital functions. Table 3. Symbol Pin description LBGA256 Reset state [1] Type Description Multiplexed digital pins P0_0[2] L3 I; PU I/O I/O I P0_1[2] M2 I; PU I/O I/O I GPIO0[0] -- General purpose digital input/output pin. SSP1_MISO -- Master In Slave Out for SSP1. ENET_RXD1 -- Ethernet receive data 1 (RMII/MII interface). n.c. GPIO0[1] -- General purpose digital input/output pin. SSP1_MOSI -- Master Out Slave in for SSP1. ENET_COL -- Ethernet Collision detect (MII interface). n.c. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 6 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P1_0[2] P2 I; PU I/O I I/O - GPIO0[4] -- General purpose digital input/output pin. CTIN_3 -- SCT input 3. Capture input 1 of timer 1. EXTBUS_A5 -- External memory address line 5. n.c. GPIO0[8] -- General purpose digital input/output pin. CTOUT_7 -- SCT output 7. Match output 3 of timer 1. EXTBUS_A6 -- External memory address line 6. Boot control pin 0 (see Table 5). n.c. GPIO0[9] -- General purpose digital input/output pin. CTOUT_6 -- SCT output 6. Match output 2 of timer 1. EXTBUS_A7 -- External memory address line 7. Boot control pin 1 (see Table 5). n.c. GPIO0[10] -- General purpose digital input/output pin. CTOUT_8 -- SCT output 8. Match output 0 of timer 2. n.c. EXTBUS_OE -- LOW active Output Enable signal. GPIO0[11] -- General purpose digital input/output pin. CTOUT_9 -- SCT output 9. Match output 1 of timer 2. n.c. EXTBUS_BLS0 -- LOW active Byte Lane select signal 0. GPIO1[8] -- General purpose digital input/output pin. CTOUT_10 -- SCT output 10. Match output 2 of timer 2. n.c. EXTBUS_CS0 -- LOW active Chip Select 0 signal. GPIO1[9] -- General purpose digital input/output pin. CTIN_5 -- SCT input 5. Capture input 2 of timer 2. n.c. EXTBUS_WE -- LOW active Write Enable signal. GPIO1[0] -- General purpose digital input/output pin. U1_DSR -- Data Set Ready input for UART1. CTOUT_13 -- SCT output 13. Match output 1 of timer 3. EXTBUS_D0 -- External memory data line 0. GPIO1[1] -- General purpose digital input/output pin. U1_DTR -- Data Terminal Ready output for UART1. CTOUT_12 -- SCT output 12. Match output 0 of timer 3. EXTBUS_D1 -- External memory data line 1. P1_1[2] R2 I; PU I/O O I/O - P1_2[2] R3 I; PU I/O O I/O - P1_3[2] P5 I; PU I/O O O P1_4[2] T3 I; PU I/O O O P1_5[2] R5 I; PU I/O O O P1_6[2] T4 I; PU I/O I O P1_7[2] T5 I; PU I/O I O I/O P1_8[2] R7 I; PU I/O O O I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 7 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P1_9[2] T7 I; PU I/O O O I/O GPIO1[2] -- General purpose digital input/output pin. U1_RTS -- Request to Send output for UART1. CTOUT_11 -- SCT output 11. Match output 3 of timer 2. EXTBUS_D2 -- External memory data line 2. GPIO1[3] -- General purpose digital input/output pin. U1_RI -- Ring Indicator input for UART1. CTOUT_14 -- SCT output 14. Match output 2 of timer 3. EXTBUS_D3 -- External memory data line 3. GPIO1[4] -- General purpose digital input/output pin. U1_CTS -- Clear to Send input for UART1. CTOUT_15 -- SCT output 15. Match output 3 of timer 3. EXTBUS_D4 -- External memory data line 4. GPIO1[5] -- General purpose digital input/output pin. U1_DCD -- Data Carrier Detect input for UART1. n.c. EXTBUS_D5 -- External memory data line 5. GPIO1[6] -- General purpose digital input/output pin. U1_TXD -- Transmitter output for UART1. n.c. EXTBUS_D6 -- External memory data line 6. GPIO1[7] -- General purpose digital input/output pin. U1_RXD -- Receiver input for UART1. n.c. EXTBUS_D7 -- External memory data line 7. GPIO0[2] -- General purpose digital input/output pin. U2_TXD -- Transmitter output for UART2. n.c. ENET_RXD0 -- Ethernet receive data 0 (RMII/MII interface). GPIO0[3] -- General purpose digital input/output pin. U2_RXD -- Receiver input for UART2. n.c. ENET_CRS (ENET_CRS_DV) -- Ethernet Carrier Sense (MII interface) or Ethernet Carrier Sense/Data Valid (RMII interface). GPIO0[12] -- General purpose digital input/output pin. U2_UCLK -- Serial clock input/output for UART2 in synchronous mode. n.c. ENET_MDIO -- Ethernet MIIM data input and output. P1_10[2] R8 I; PU I/O I O I/O P1_11[2] T9 I; PU I/O I O I/O P1_12[2] R9 I; PU I/O I I/O P1_13[2] R10 I; PU I/O O I/O P1_14[2] R11 I; PU I/O I I/O P1_15[2] T12 I; PU I/O O I P1_16[2] M7 I; PU I/O I I P1_17[2] M8 I; PU I/O I/O I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 8 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P1_18[2] N12 I; PU I/O I/O O GPIO0[13] -- General purpose digital input/output pin. U2_DIR -- RS-485/EIA-485 output enable/direction control for UART2. n.c. ENET_TXD0 -- Ethernet transmit data 0 (RMII/MII interface). ENET_TX_CLK (ENET_REF_CLK) -- Ethernet Transmit Clock (MII interface) or Ethernet Reference Clock (RMII interface). SSP1_SCK -- Serial clock for SSP1. n.c. n.c. GPIO0[15] -- General purpose digital input/output pin. SSP1_SSEL -- Slave Select for SSP1. n.c. ENET_TXD1 -- Ethernet transmit data 1 (RMII/MII interface). n.c. U0_TXD -- Transmitter output for USART0. EXTBUS_A13 -- External memory address line 13. USB0_PWR_EN -- VBUS drive signal (towards external charge pump or power management unit); indicates that Vbus must be driven (active high). n.c. U0_RXD -- Receiver input for USART0. EXTBUS_A12 -- External memory address line 12. USB0_PWR_FAULT -- Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). n.c. U0_UCLK -- Serial clock input/output for USART0 in synchronous mode. EXTBUS_A11 -- External memory address line 11. USB0_IND1 -- USB0 port indicator LED control output 1. n.c. I2C1_SDA -- I2C1 data input/output (this pin does not use a specialized I2C pad). U3_TXD -- Transmitter output for USART3. CTIN_1 -- SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2. n.c. I2C1_SCL -- I2C1 clock input/output (this pin does not use a specialized I2C pad). U3_RXD -- Receiver input for USART3. CTIN_0 -- SCT input 0. Capture input 0 of timer 0, 1, 2, 3. P1_19[2] M11 I I/O - P1_20[2] M10 I; PU I/O I/O O P2_0[2] T16 O I/O O P2_1[2] N15 I I/O O P2_2[2] M15 I/O I/O O P2_3[2] J12 I/O O I P2_4[2] K11 I/O I I LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 9 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P2_5[3] K14 I I I n.c. CTIN_2 -- SCT input 2. Capture input 2 of timer 0. USB1_VBUS -- Monitors the presence of USB1 bus power. Note: This signal must be HIGH for USB reset to occur. ADCTRIG1 -- ADC trigger input 1. n.c. U0_DIR -- RS-485/EIA-485 output enable/direction control for USART0. EXTBUS_A10 -- External memory address line 10. USB0_IND0 -- USB0 port indicator LED control output 0. GPIO0[7] -- General purpose digital input/output pin. This pin is sampled at RESET for ISP entry. CTOUT_1 -- SCT output 1. Match output 1 of timer 0. U3_UCLK -- Serial clock input/output for USART3 in synchronous mode. EXTBUS_A9 -- External memory address line 9. n.c. CTOUT_0 -- SCT output 0. Match output 0 of timer 0. U3_DIR -- RS-485/EIA-485 output enable/direction control for USART3. EXTBUS_A8 -- External memory address line 8. Boot control pin 2 (see Table 5). GPIO1[10] -- General purpose digital input/output pin. CTOUT_3 -- SCT output 3. Match output 3 of timer 0. U3_BAUD3 -- All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. P2_6[2] K16 I/O I/O O P2_7[2] H14 I; PU I/O O I/O I/O P2_8[2] J16 O I/O I/O P2_9[2] H16 I; PU I/O O I/O I/O P2_10[2] G16 I; PU I/O O O I/O P2_11[2] F16 I; PU I/O O I I/O P2_12[2] E15 I; PU I/O O I/O P2_13[2] C16 I; PU I/O I I/O LPC1850_30_20_10 Objective data sheet Rev. 1 -- 3 January 2011 10 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P3_0[2] F13 I/O O I/O O I2S_RX_SCK -- Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I2S_RX_MCLK -- I2S receive master clock. I2S_TX_SCK -- I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I2S_TX_MCLK -- I2S transmit master clock. I2S_TX_WS -- Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I2S_RX_WS -- Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. CAN1_RD -- CAN1 receiver input. USB1_IND1 -- USB1 port indicator LED control output 1. I2S_TX_SDA -- I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I2S_RX_SDA -- I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. CAN1_TD -- CAN1 transmitter output. USB1_IND0 -- USB1 port indicator LED control output 0. n.c. n.c. SSP0_SCK -- Serial clock for SSP0. SPIFI_SCK -- Serial clock for SPIFI. GPIO1[14] -- General purpose digital input/output pin. n.c. n.c. SPIFI_SIO3 -- I/O lane 3 for SPIFI. GPIO1[15] -- General purpose digital input/output pin. n.c. n.c. SPIFI_SIO2 -- I/O lane 2 for SPIFI. GPIO0[6] -- General purpose digital input/output pin. n.c. SSP0_SSEL -- Slave Select for SSP0. SPIFI_MISO -- Input I1 in SPIFI quad mode; SPIFI output IO1. n.c. n.c. SSP0_MISO -- Master In Slave Out for SSP0. SPIFI_MOSI -- Input I0 in SPIFI quad mode; SPIFI output IO0. P3_1[2] G11 I/O I/O I O P3_2[2] F11 I/O I/O O O P3_3[2] B14 I/O O P3_4[2] A15 I; PU I/O I/O P3_5[2] C12 I; PU I/O I/O P3_6[2] B13 I; PU I/O I/O I/O P3_7[2] C11 I/O I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 11 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P3_8[2] C10 I/O I/O n.c. n.c. SSP0_MOSI -- Master Out Slave in for SSP0. SPIFI_CS -- SPIFI serial flash chip select. GPIO2[0] -- General purpose digital input/output pin. MCOA0 -- Motor control PWM channel 0, output A. NMI -- External interrupt input to NMI. n.c. GPIO2[1] -- General purpose digital input/output pin. CTOUT_1 -- SCT output 1. Match output 1 of timer 0. LCDVD0 -- LCD data. n.c. GPIO2[2] -- General purpose digital input/output pin. CTOUT_0 -- SCT output 0. Match output 0 of timer 0. LCDVD3 -- LCD data. n.c. GPIO2[3] -- General purpose digital input/output pin. CTOUT_3 -- SCT output 0. Match output 3 of timer 0. LCDVD2 -- LCD data. n.c. GPIO2[4] -- General purpose digital input/output pin. CTOUT_2 -- SCT output 2. Match output 2 of timer 0. LCDVD1 -- LCD data. n.c. GPIO2[5] -- General purpose digital input/output pin. CTOUT_5 -- SCT output 5. Match output 1 of timer 1. LCDFP -- Frame pulse (STN). Vertical synchronization pulse (TFT). n.c. GPIO2[6] -- General purpose digital input/output pin. CTOUT_4 -- SCT output 4. Match output 0 of timer 1. LCDENAB/LCDM -- STN AC bias drive or TFT data enable input. n.c. LCDDCLK -- LCD panel clock. GP_CLKIN -- General purpose clock input to the CGU. n.c. n.c. P4_0[2] D5 I; PU I/O O I - P4_1[2] A1 I; PU I/O O O - P4_2[2] D3 I; PU I/O O O - P4_3[2] C2 I; PU I/O O O - P4_4[2] B1 I; PU I/O O O - P4_5[2] D2 I; PU I/O O O - P4_6[2] C1 I; PU I/O O O - P4_7[2] H4 O I - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 12 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P4_8[2] E2 I O - n.c. CTIN_5 -- SCT input 5. Capture input 2 of timer 2. LCDVD9 -- LCD data. n.c. n.c. CTIN_6 -- SCT input 6. Capture input 1 of timer 3. LCDVD11 -- LCD data. n.c. n.c. CTIN_2 -- SCT input 2. Capture input 2 of timer 0. LCDVD10 -- LCD data. n.c. GPIO2[9] -- General purpose digital input/output pin. MCOB2 -- Motor control PWM channel 2, output B. EXTBUS_D12 -- External memory data line 12. n.c. GPIO2[10] -- General purpose digital input/output pin. MCI2 -- Motor control PWM channel 2, input. EXTBUS_D13 -- External memory data line 13. n.c. GPIO2[11] -- General purpose digital input/output pin. MCI1 -- Motor control PWM channel 1, input. EXTBUS_D14 -- External memory data line 14. n.c. GPIO2[12] -- General purpose digital input/output pin. MCI0 -- Motor control PWM channel 0, input. EXTBUS_D15 -- External memory data line 15. n.c. GPIO2[13] -- General purpose digital input/output pin. MCOB0 -- Motor control PWM channel 0, output B. EXTBUS_D8 -- External memory data line 8. n.c. GPIO2[14] -- General purpose digital input/output pin. MCOA1 -- Motor control PWM channel 1, output A. EXTBUS_D9 -- External memory data line 9. n.c. P4_9[2] L2 I O - P4_10[2] M3 I O - P5_0[2] N3 I; PU I/O O I/O - P5_1[2] P3 I; PU I/O I I/O - P5_2[2] R4 I; PU I/O I I/O - P5_3[2] T8 I; PU I/O I I/O - P5_4[2] P9 I; PU I/O O I/O - P5_5[2] P10 I; PU I/O O I/O - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 13 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P5_6[2] T13 I; PU I/O O I/O - GPIO2[15] -- General purpose digital input/output pin. MCOB1 -- Motor control PWM channel 1, output B. EXTBUS_D10 -- External memory data line 10. n.c. GPIO2[7] -- General purpose digital input/output pin. MCOA2 -- Motor control PWM channel 2, output A. EXTBUS_D11 -- External memory data line 11. n.c. I2S_RX_SCK -- Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I2S_RX_MCLK -- I2S receive master clock. n.c. n.c. GPIO3[0] -- General purpose digital input/output pin. EXTBUS_DYCS1 -- SDRAM chip select 1. U0_UCLK -- Serial clock input/output for USART0 in synchronous mode. I2S_RX_WS -- Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. GPIO3[1] -- General purpose digital input/output pin. EXTBUS_CKEOUT1 -- SDRAM clock enable 1. U0_DIR -- RS-485/EIA-485 output enable/direction control for USART0. I2S_RX_SDA -- I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. GPIO3[2] -- General purpose digital input/output pin. USB0_PWR_EN -- VBUS drive signal (towards external charge pump or power management unit); indicates that Vbus must be driven (active high). n.c. EXTBUS_CS1 -- LOW active Chip Select 1 signal. GPIO3[3] -- General purpose digital input/output pin. CTIN_6 -- SCT input 6. Capture input 1 of timer 3. U0_TXD -- Transmitter output for USART0. EXTBUS_CAS -- LOW active SDRAM Column Address Strobe. GPIO3[4] -- General purpose digital input/output pin. CTOUT_6 -- SCT output 6. Match output 2 of timer 1. U0_RXD -- Receiver input for USART0. EXTBUS_RAS -- LOW active SDRAM Row Address Strobe. P5_7[2] R12 I; PU I/O O I/O - P6_0 M12 I/O O - P6_1[2] R15 I; PU I/O O I/O I/O P6_2[2] L13 I; PU I/O O I/O I/O P6_3[2] P15 I; PU I/O O O P6_4[2] R16 I; PU I/O I O O P6_5[2] P16 I; PU I/O O I O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 14 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P6_6[2] L14 I; PU I/O O O GPIO0[5] -- General purpose digital input/output pin. EXTBUS_BLS1 -- LOW active Byte Lane select signal 1. n.c. USB0_PWR_FAULT -- Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). n.c. EXTBUS_A15 -- External memory address line 15. n.c. USB0_IND1 -- USB0 port indicator LED control output 1. n.c. EXTBUS_A14 -- External memory address line 14. n.c. USB0_IND0 -- USB0 port indicator LED control output 0. GPIO3[5] -- General purpose digital input/output pin. n.c. n.c. EXTBUS_DYCS0 -- SDRAM chip select 0. GPIO3[6] -- General purpose digital input/output pin. MCABORT -- Motor control PWM, LOW-active fast abort. n.c. EXTBUS_DQMOUT1 -- Data mask 1 used with SDRAM and static devices. GPIO3[7] -- General purpose digital input/output pin. n.c. n.c. EXTBUS_CKEOUT0 -- SDRAM clock enable 0. GPIO2[8] -- General purpose digital input/output pin. CTOUT_7 -- SCT output 7. Match output 3 of timer 1. n.c. EXTBUS_DQMOUT0 -- Data mask 0 used with SDRAM and static devices. GPIO3[8] -- General purpose digital input/output pin. CTOUT_14 -- SCT output 14. Match output 2 of timer 3. n.c. LCDLE -- Line end signal. GPIO3[9] -- General purpose digital input/output pin. CTOUT_15 -- SCT output 15. Match output 3 of timer 3. I2S_TX_WS -- Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. LCDVD19 -- LCD data. P6_7[2] J13 I/O O P6_8[2] H13 I/O O P6_9[2] J15 I; PU I/O O P6_10[2] H15 I; PU I/O O O P6_11[2] H12 I; PU I/O O P6_12[2] G15 I; PU I/O O O P7_0[2] B16 I; PU I/O O O P7_1[2] C14 I; PU I/O O I/O O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 15 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P7_2[2] A16 I; PU I/O I I/O O GPIO3[10] -- General purpose digital input/output pin. CTIN_4 -- SCT input 4. Capture input 2 of timer 1. I2S_TX_SDA -- I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. LCDVD18 -- LCD data. GPIO3[11] -- General purpose digital input/output pin. CTIN_3 -- SCT input 3. Capture input 1 of timer 1. n.c. LCDVD17 -- LCD data. GPIO3[12] -- General purpose digital input/output pin. CTOUT_13 -- SCT output 13. Match output 1 of timer 3. n.c. LCDVD16 -- LCD data. GPIO3[13] -- General purpose digital input/output pin. CTOUT_12 -- SCT output 12. Match output 0 of timer 3. n.c. LCDVD8 -- LCD data. GPIO3[14] -- General purpose digital input/output pin. CTOUT_11 -- SCT output 1. Match output 3 of timer 2. n.c. LCDLP -- Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). GPIO3[15] -- General purpose digital input/output pin. CTOUT_8 -- SCT output 8. Match output 0 of timer 2. n.c. LCDPWR -- LCD panel power enable. GPIO4[0] -- General purpose digital input/output pin. USB0_PWR_FAULT -- Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). n.c. MCI2 -- Motor control PWM channel 2, input. GPIO4[1] -- General purpose digital input/output pin. USB0_IND1 -- USB0 port indicator LED control output 1. n.c. MCI1 -- Motor control PWM channel 1, input. GPIO4[2] -- General purpose digital input/output pin. USB0_IND0 -- USB0 port indicator LED control output 0. n.c. MCI0 -- Motor control PWM channel 0, input. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. P7_3[2] C13 I; PU I/O I O P7_4[2] C8 I; PU I/O O O P7_5[2] A7 I; PU I/O O O P7_6[2] C7 I; PU I/O O O P7_7[2] B6 I; PU I/O O O P8_0[2] E5 I; PU I/O O I P8_1[2] H5 I; PU I/O O I P8_2[2] K4 I; PU I/O O I LPC1850_30_20_10 Objective data sheet Rev. 1 -- 3 January 2011 16 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P8_3[2] J3 I; PU I/O I/O O GPIO4[3] -- General purpose digital input/output pin. USB1_ULPI_D2 -- ULPI link bidirectional data line 2. n.c. LCDVD12 -- LCD data. GPIO4[4] -- General purpose digital input/output pin. USB1_ULPI_D1 -- ULPI link bidirectional data line 1. n.c. LCDVD7 -- LCD data. GPIO4[5] -- General purpose digital input/output pin. USB1_ULPI_D0 -- ULPI link bidirectional data line 0. n.c. LCDVD6 -- LCD data. GPIO4[6] -- General purpose digital input/output pin. USB1_ULPI_NXT -- ULPI link NXT signal. Data flow control signal from the PHY. n.c. LCDVD5 -- LCD data. GPIO4[7] -- General purpose digital input/output pin. USB1_ULPI_STP -- ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. n.c. LCDVD4 -- LCD data. n.c. USB1_ULPI_CLK -- ULPI link CLK signal. 60 MHz clock generated by the PHY. n.c. n.c. GPIO4[12] -- General purpose digital input/output pin. MCABORT -- Motor control PWM, LOW-active fast abort. n.c. n.c. GPIO4[13] -- General purpose digital input/output pin. MCOA2 -- Motor control PWM channel 2, output A. n.c. n.c. GPIO4[14] -- General purpose digital input/output pin. MCOB2 -- Motor control PWM channel 2, output B. n.c. n.c. P8_4[2] J2 I; PU I/O I/O O P8_5[2] J1 I; PU I/O I/O O P8_6[2] K3 I; PU I/O I O P8_7[2] K1 I; PU I/O O O P8_8[2] L1 I - P9_0[2] T1 I; PU I/O O - P9_1[2] N6 I; PU I/O O - P9_2[2] N8 I; PU I/O O - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 17 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description P9_3[2] M6 I; PU I/O O O - GPIO4[15] -- General purpose digital input/output pin. MCOA0 -- Motor control PWM channel 0, output A. USB1_IND1 -- USB1 Port indicator LED control output 1. n.c. n.c. MCOB0 -- Motor control PWM channel 0, output B. USB1_IND0 -- USB1 Port indicator LED control output 0. n.c. n.c. MCOA1 -- Motor control PWM channel 1, output A. USB1_VBUS_EN -- USB1 VBUS power enable. n.c. GPIO4[11] -- General purpose digital input/output pin. MCOB1 -- Motor control PWM channel 1, output B. USB1_PWR_FAULT -- USB1 Port power fault signal indicating over-current condition; this signal monitors over-current on the USB1 bus (external circuitry required to detect over-current condition). n.c. n.c. SPIFI_SCK -- Serial clock for SPIFI. n.c. n.c. GPIO4[8] -- General purpose digital input/output pin. QEI_IDX -- Quadrature Encoder Interface INDEX input. n.c. n.c. GPIO4[9] -- General purpose digital input/output pin. QEI_PHB -- Quadrature Encoder Interface PHB input. n.c. n.c. GPIO4[10] -- General purpose digital input/output pin. QEI_PHA -- Quadrature Encoder Interface PHA input. n.c. SPIFI_SIO3 -- I/O lane 3 for SPIFI. n.c. CTOUT_9 -- SCT output 9. Match output 1 of timer 2. n.c. EXTBUS_A23 -- External memory address line 23. P9_4[2] N10 O O - P9_5[2] M9 O O - P9_6[2] L11 I; PU I/O O O PA_0[2] L12 LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 18 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description PB_0[2] B15 O O - n.c. CTOUT_10 -- SCT output 10. Match output 2 of timer 2. LCDVD23 -- LCD data. n.c. n.c. USB1_ULPI_DIR -- ULPI link DIR signal. Controls the ULP data line direction. LCDVD22 -- LCD data. n.c. n.c. USB1_ULPI_D7 -- ULPI link bidirectional data line 7. LCDVD21 -- LCD data. n.c. n.c. USB1_ULPI_D6 -- ULPI link bidirectional data line 6. LCDVD20 -- LCD data. n.c. n.c. USB1_ULPI_D5 -- ULPI link bidirectional data line 5. LCDVD15 -- LCD data. n.c. n.c. USB1_ULPI_D4 -- ULPI link bidirectional data line 4. LCDVD14 -- LCD data. n.c. n.c. USB1_ULPI_D3 -- ULPI link bidirectional data line 3. LCDVD13 -- LCD data. n.c. ENET_RX_CLK (ENET_REF_CLK) -- Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface). USB1_ULPI_CLK -- ULPI link CLK signal. 60 MHz clock generated by the PHY. n.c. SDIO_CLK -- SD/MMC card clock. USB1_ULPI_D7 -- ULPI link bidirectional data line 7. SDIO_VOLT0 -- SD/MMC bus voltage select output 0. U1_RI -- Ring Indicator input for UART 1. ENET_MDC -- Ethernet MIIM clock. PB_1[2] A14 I O - PB_2[2] B12 I/O O - PB_3[2] A13 I/O O - PB_4[2] B11 I/O O - PB_5[2] A12 I/O O - PB_6[2] A6 I/O O - PC_0[2] D4 I/O I I/O PC_1[2] E4 I/O O I O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 19 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description PC_2[2] F6 I/O O I O USB1_ULPI_D6 -- ULPI link bidirectional data line 6. SDIO_RST -- SD/MMC reset signal for MMC4.4 card. U1_CTS -- Clear to Send input for UART 1. ENET_TXD2 -- Ethernet transmit data 2 (MII interface). USB1_ULPI_D5 -- ULPI link bidirectional data line 5. SDIO_VOLT1 -- SD/MMC bus voltage select output 1. U1_RTS -- Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. ENET_TXD3 -- Ethernet transmit data 3 (MII interface). SDIO_D0 -- SD/MMC data bus line 0. USB1_ULPI_D4 -- ULPI link bidirectional data line 4. SPIFI_CS -- SPIFI serial flash chip select. ENET_TX_EN -- Ethernet transmit data enable (RMII/MII interface). SDIO_D1 -- SD/MMC data bus line 1. USB1_ULPI_D3 -- ULPI link bidirectional data line 3. SPIFI_MISO -- Input I1 in SPIFI quad mode; SPIFI output IO1. ENET_TX_ER -- Ethernet Transmit Error (MII interface). SDIO_D2 -- SD/MMC data bus line 2. USB1_ULPI_D2 -- ULPI link bidirectional data line 2. n.c. ENET_RXD2 -- Ethernet receive data 2 (RMII/MII interface). SDIO_D3 -- SD/MMC data bus line 3. USB1_ULPI_D1 -- ULPI link bidirectional data line 1. n.c. ENET_RXD3 -- Ethernet receive data 3 (RMII/MII interface). SDIO_CD -- SD/MMC card detect input. USB1_ULPI_D0 -- ULPI link bidirectional data line 0. SPIFI_SIO2 -- I/O lane 2 for SPIFI. ENET_RX_DV -- Ethernet Receive Data Valid (MII interface). SDIO_POW -- PC_3[2] F5 I/O O O O PC_4[2] F4 I/O I/O I/O O PC_5[2] G4 I/O I/O I/O O PC_6[2] H6 I/O I/O I PC_7[2] G5 I/O I/O I PC_8[2] N4 I I/O I/O I PC_9[2] K2 O I I PC_10[2] M5 I/O O I - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 20 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description PC_11[2] L5 I/O I I - SDIO_D4 -- SD/MMC data bus line 4. USB1_ULPI_DIR -- ULPI link DIR signal. Controls the ULP data line direction. U1_DCD -- Data Carrier Detect input for UART 1. n.c. SDIO_D5 -- SD/MMC data bus line 5. n.c. U1_DTR -- Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. n.c. SDIO_D6 -- SD/MMC data bus line 6. n.c. U1_TXD -- Transmitter output for UART 1. n.c. SDIO_D7 -- SD/MMC data bus line 7. n.c. U1_RXD -- Receiver input for UART 1. n.c. n.c. CTOUT_15 -- SCT output 15. Match output 3 of timer 3. EXTBUS_DQMOUT2 -- Data mask 2 used with SDRAM and static devices. n.c. n.c. n.c. EXTBUS_CKEOUT2 -- SDRAM clock enable 2. n.c. n.c. CTOUT_7 -- SCT output 7. Match output 3 of timer 1. EXTBUS_D16 -- External memory data line 16. n.c. n.c. CTOUT_6 -- SCT output 7. Match output 2 of timer 1. EXTBUS_D17 -- External memory data line 17. n.c. n.c. CTOUT_8 -- SCT output 8. Match output 0 of timer 2. EXTBUS_D18 -- External memory data line 18. n.c. PC_12[2] L6 I/O O - PC_13[2] M1 I/O O - PC_14[2] N1 I/O I - PD_0[2] N2 O O - PD_1[2] P1 O - PD_2[2] R1 O I/O - PD_3[2] P4 O I/O - PD_4[2] T2 O I/O - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 21 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description PD_5[2] P6 O I/O - n.c. CTOUT_9 -- SCT output 9. Match output 1 of timer 2. EXTBUS_D19 -- External memory data line 19. n.c. n.c. CTOUT_10 -- SCT output 10. Match output 2 of timer 2. EXTBUS_D20 -- External memory data line 20. n.c. n.c. CTIN_5 -- SCT input 5. Capture input 2 of timer 2. EXTBUS_D21 -- External memory data line 21. n.c. n.c. CTIN_6 -- SCT input 6. Capture input 1 of timer 3. EXTBUS_D22 -- External memory data line 22. n.c. n.c. CTOUT_13 -- SCT output 13. Match output 1 of timer 3. EXTBUS_D23 -- External memory data line 23. n.c. n.c. CTIN_1 -- SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2. EXTBUS_BLS3 -- LOW active Byte Lane select signal 3. n.c. n.c. n.c. EXTBUS_CS3 -- LOW active Chip Select 3 signal. n.c. n.c. n.c. EXTBUS_CS2 -- LOW active Chip Select 2 signal. n.c. n.c. CTIN_0 -- SCT input 0. Capture input 0 of timer 0, 1, 2, 3. EXTBUS_BLS2 -- LOW active Byte Lane select signal 2. n.c. PD_6[2] R6 O I/O - PD_7[2] T6 I I/O - PD_8[2] P8 I I/O - PD_9[2] T11 O I/O - PD_10[2] P11 I O - PD_11[2] N9 O - PD_12[2] N11 O - PD_13[2] T14 I O - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 22 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description PD_14[2] R13 O - n.c. n.c. EXTBUS_DYCS2 -- SDRAM chip select 2. n.c. n.c. n.c. EXTBUS_A17 -- External memory address line 17. n.c. n.c. n.c. EXTBUS_A16 -- External memory address line 16. n.c. n.c. n.c. n.c. EXTBUS_A18 -- External memory address line 18. n.c. n.c. n.c. EXTBUS_A19 -- External memory address line 19. ADCTRIG0 -- ADC trigger input 0. CAN1_RD -- CAN1 receiver input. SPIFI_MOSI -- Input I0 in SPIFI quad mode; SPIFI output IO0. EXTBUS_A20 -- External memory address line 20. n.c. CAN1_TD -- CAN1 transmitter output. ADCTRIG1 -- ADC trigger input 1. EXTBUS_A21 -- External memory address line 21. n.c. NMI -- External interrupt input to NMI. n.c. EXTBUS_A22 -- External memory address line 22. n.c. CTOUT_3 -- SCT output 3. Match output 3 of timer 0. U1_RTS -- Request to Send output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. EXTBUS_D24 -- External memory data line 24. PD_15[2] T15 I/O - PD_16[2] R14 I/O - PE_0[2] P14 I/O PE_1[2] N14 I/O PE_2[2] M14 I I I/O I/O PE_3[2] K12 O I I/O PE_4[2] K13 I I/O PE_5[2] N16 O O I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 23 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description PE_6[2] M16 O I I/O n.c. CTOUT_2 -- SCT output 2. Match output 2 of timer 0. U1_RI -- Ring Indicator input for UART 1. EXTBUS_D25 -- External memory data line 25. n.c. CTOUT_5 -- SCT output 5. Match output 1 of timer 1. U1_CTS -- Clear to Send input for UART1. EXTBUS_D26 -- External memory data line 26. n.c. CTOUT_4 -- SCT output 4. Match output 0 of timer 0. U1_DSR -- Data Set Ready input for UART 1. EXTBUS_D27 -- External memory data line 27. n.c. CTIN_4 -- SCT input 4. Capture input 2 of timer 1. U1_DCD -- Data Carrier Detect input for UART 1. EXTBUS_D28 -- External memory data line 28. n.c. CTIN_3 -- SCT input 3. Capture input 1 of timer 1. U1_DTR -- Data Terminal Ready output for UART 1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART 1. EXTBUS_D29 -- External memory data line 29. n.c. CTOUT_12 -- SCT output 12. Match output 0 of timer 3. U1_TXD -- Transmitter output for UART 1. EXTBUS_D30 -- External memory data line 30. n.c. CTOUT_11 -- SCT output 11. Match output 3 of timer 2. U1_RXD -- Receiver input for UART 1. EXTBUS_D31 -- External memory data line 31. n.c. CTOUT_14 -- SCT output 14. Match output 2 of timer 3. I2C1_SDA -- I2C1 data input/output (this pin does not use a specialized I2C pad). EXTBUS_DQMOUT3 -- Data mask 3 used with SDRAM and static devices. n.c. n.c. n.c. EXTBUS_DYCS3 -- SDRAM chip select 3. PE_7[2] F15 O I I/O PE_8[2] F14 O I I/O PE_9[2] E16 I I I/O PE_10[2] E14 I O I/O PE_11[2] D16 O O I/O PE_12[2] D15 O I I/O PE_13[2] G14 O I/O O PE_14[2] C15 O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 24 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description PE_15[2] E13 O I/O O n.c. CTOUT_0 -- SCT output 0. Match output 0 of timer 0. I2C1_SCL -- I2C1 clock input/output (this pin does not use a specialized I2C pad). EXTBUS_CKEOUT3 -- SDRAM clock enable 3. SSP0_SCK -- Serial clock for SSP0. n.c. n.c. n.c. n.c. n.c. SSP0_SSEL -- Slave Select for SSP0. n.c. n.c. U3_TXD -- Transmitter output for USART3. SSP0_MISO -- Master In Slave Out for SSP0. n.c. n.c. U3_RXD -- Receiver input for USART3. SSP0_MOSI -- Master Out Slave in for SSP0. n.c. SSP1_SCK -- Serial clock for SSP1. GP_CLKIN -- General purpose clock input to the CGU. TRACECLK -- Trace clock. n.c. n.c. U3_UCLK -- Serial clock input/output for USART3 in synchronous mode. SSP1_SSEL -- Slave Select for SSP1. TRACEDATA[0] -- Trace data, bit 0. n.c. U3_DIR -- RS-485/EIA-485 output enable/direction control for USART3. SSP1_MISO -- Master In Slave Out for SSP1. TRACEDATA[1] -- Trace data, bit 1. n.c. U3_BAUD -- PF_0[2] D12 I/O - PF_1[2] E11 I/O - PF_2[2] D11 O I/O - PF_3[2] E10 I I/O - PF_4[2] D10 I/O I O - PF_5[2] E9 I/O I/O O PF_6[2] E7 I/O I/O O PF_7[2] B7 I/O I/O O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 25 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description PF_8[2] E6 I/O I O n.c. U0_UCLK -- Serial clock input/output for USART0 in synchronous mode. CTIN_2 -- SCT input 2. Capture input 2 of timer 0. TRACEDATA[3] -- Trace data, bit 3. n.c. U0_DIR -- RS-485/EIA-485 output enable/direction control for USART0. CTOUT_1 -- SCT output 1. Match output 1 of timer 0. n.c. n.c. U0_TXD -- Transmitter output for USART0. SDIO_WP -- SD/MMC card write protect input. n.c. n.c. U0_RXD -- Receiver input for USART0. SDIO_VOLT2 -- SD/MMC bus voltage select output 2. n.c. EXTBUS_CLK0 -- SDRAM clock 0. CLKOUT -- Clock output pin. n.c. n.c. EXTBUS_CLK1 -- SDRAM clock 1. CLKOUT -- Clock output pin. n.c. n.c. EXTBUS_CLK3 -- SDRAM clock 3. CLKOUT -- Clock output pin. n.c. n.c. EXTBUS_CLK2 -- SDRAM clock 2. CLKOUT -- Clock output pin. n.c. n.c. JTAG interface control signal. Also used for boundary scan. Test Clock for JTAG interface (default) or Serial Wire (SW) clock. Test Reset for JTAG interface. Test Mode Select for JTAG interface (default) or SW debug data input/output. Test Data Out for JTAG interface (default) or SW trace output. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. PF_9[2] D6 I/O O - PF_10[2] A3 O I - PF_11[2] A2 I O - Clock pins CLK0[4] N5 LPC1850_30_20_10 L4 J5 M4 K6 K5 I I I I O Objective data sheet Rev. 1 -- 3 January 2011 26 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description TDI[2] I2C-bus pins I2C0_SCL[8] I2C0_SDA[8] USB0 pins USB0_DP[5] USB0_DM[5] USB0_VBUS[5] USB0_ID[6] USB0_RREF[6] USB1 pins USB1_DP[7] USB1_DM[7] RESET[9] J4 L15 L16 F2 G2 F1 H2 H1 F12 G12 D9 I I/O I/O I/O I/O I/O I Test Data In for JTAG interface. I2C clock input/output. Open-drain output (for I2C-bus compliance). I2C data input/output. Open-drain output (for I2C-bus compliance). USB0 bidirectional D+ line. USB0 bidirectional D- line. VBUS pin (power on USB cable). Indicates to the transceiver whether connected a A-device (ID LOW) or B-device (ID HIGH). 12.0 k (accuracy 1 %) on-board resistor to ground for current reference. I/O I/O I USB1 bidirectional D+ line. USB1 bidirectional D- line. External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. ADC0/1 input channel 0. Shared between ADC0, ADC1, and DAC. ADC0/1 input channel 1. ADC0/1 input channel 2. ADC0/1 input channel 3. ADC0/1 input channel 4. ADC0/1 input channel 5. ADC0/1 input channel 6. ADC0/1 input channel 7. RTC controlled output. Input to the RTC 32 kHz ultra-low power oscillator circuit. Output from the RTC 32 kHz ultra-low power oscillator circuit. Reset and wake-up pins WAKEUP0[9] WAKEUP1 WAKEUP2 WAKEUP3 ADC pins ADC0[6] ADC1[6] ADC2[6] ADC3[6] ADC4[6] ADC5[6] ADC6[6] ADC7[6] RTC RTC_ALARM RTCX1 RTCX2 XTAL1[6] LPC1850_30_20_10 A9 A10 C9 D8 I I I I E3 C3 A4 B5 C6 B3 A5 C5 A11 A8 B8 D1 Crystal oscillator pins Input to the oscillator circuit and internal clock generator circuits. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 27 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description XTAL2[6] USB0_VDDA3V3_ DRIVER USB0_VDDA3V3 USB0_VSSA_TERM USB0_VSSA_REF VDDA VBAT VDDREG E1 F3 G3 H3 G1 B4 B10 F10; F9; L8; L7; E8 F7; J7; N7; L10; E12; N13; L9; H10; G10; D7; J6; F8; K7 B2 H7; K8; G9; J11; J10 O Output from the oscillator amplifier. Separate analog 3.3 V power supply for driver. USB 3.3 V separate power supply voltage Dedicated analog ground for clean reference for termination resistors. Dedicated clean analog ground for generation of reference currents and voltages. Analog power supply. RTC power supply: 3.3 V on this pin supplies power to the RTC. Main regulator power supply Power and ground pins VPP VDDIO OTP programming voltage I/O power supply VSSA VSS - Ground Ground LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 28 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Symbol Pin description ...continued LBGA256 Reset state [1] Type Description VSSIO G6; J8; J9; K9; K10; P7; M13; P13; D13; G8; H8; G7; C4; H9 B9 - Ground Pins not connected [1] [2] [3] [4] [5] [6] [7] [8] [9] n.c. I = input, O = output, IA = inactive; PU = pull-up enabled; F = floating Digital I/O pin. Not 5 V tolerant. Digital I/O pin. 5 V tolerant. Digital high-speed I/O pin. 5 V tolerant analog I/O pin. 3.3 V tolerant analog I/O pin. 5 V tolerant USB I/O pin. I2C-bus 5 V tolerant open-drain pin. Reset input pin; [10] Alarm output pin; LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 29 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses allow for concurrent code and data accesses from different slave ports. The LPC1850/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 7.2 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptable/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 30 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.3 AHB multilayer matrix TEST/DEBUG INTERFACE ARM CORTEX-M3 System bus I-code bus D-code bus 0 GPDMA 1 ETHERNET(1) USB0(1) USB1(1) LCD(1) SD/ MMC(1) masters slaves 32 kB ROM 64/96 kB LOCAL SRAM 40 kB LOCAL SRAM 32 kB AHB SRAM 16 kB AHB SRAM(1) 16 kB AHB SRAM EXTERNAL MEMORY CONTROLLER AHB MULTILAYER MATRIX AHB REGISTER INTERFACES, APB, RTC DOMAIN PERIPHERALS = master-slave connection 002aaf880 (1) Not available on all parts (see Table 2). Fig 3. AHB multilayer matrix master and slave connections 7.4 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.4.1 Features * * * * * * Controls system exceptions and peripheral interrupts. In the LPC1850/30/20/10, the NVIC supports 32 vectored interrupts. 32 programmable interrupt priority levels, with hardware priority level masking. Relocatable vector table. Non-Maskable Interrupt (NMI). Software interrupt generation. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 31 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.4.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 7.5 Event router The event router combines various internal signals, interrupts, and the external interrupt pins (WAKEUP[3:0]) to create an interrupt in the NVIC if enabled and to create a wake-up signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down, and Deep power-down modes. Individual events can be configured as edge or level sensitive and can be enabled or disabled in the event router. The event router can be battery powered. The following events if enabled in the event router can create a wake-up signal and/or an interrupt: * * * * * External pins WAKEUP0/1/2/3 and RESET Alarm timer, RTC, WWDT, BOD interrupts C_CAN and QEI interrupts Ethernet, USB0, USB1 signals Selected outputs of combined timers (SCT and timer0/1/3) 7.6 System Tick timer (SysTick) The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. 7.7 On-chip static RAM The LPC1850/30/20/10 support up to 200 kB SRAM with separate bus master access for higher throughput and individual power control for low power operation. 7.8 Boot ROM The internal ROM memory is used to store the boot code of the LPC1850/30/20/10. After a reset, the ARM processor will start its code execution from this memory. The boot ROM memory includes the following features: * ROM memory size is 32 kB. * Supports booting from UART interfaces and external static memory such as NOR flash, SPI flash, quad SPI flash. * Includes APIs for power control and OTP programming. * Includes SPIFI and USB drivers. AES capable parts also support: * CMAC authentication on the boot image. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 32 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller * Secure booting from an encrypted image. In development mode booting from a plain text image is possible. Development mode is terminated by programming the AES key. * API for AES programming. Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is determined by the states of the boot pins P2_8, P1_2, and P1_1. Table 4. Boot mode when OTP BOOT_SRC bits are programmed BOOT_SRC BOOT_SRC bit 2 bit 1 0 0 BOOT_SRC Description bit 0 0 Boot source is defined by the reset state of P1_1, P1_2, and P2_8 pins. See Table 5. Boot from device connected to USART0 using pins P2_0 and P2_1. Boot from Quad SPI flash connected to the SPIFI interface using pins P3_3 to P3_8. Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. Do not use this option. Do not use this option. Boot mode Boot mode defined by pin state at reset UART 0 0 1 SPIFI 0 1 0 EMC 8-bit 0 1 1 EMC 16-bit 1 0 0 EMC 32-bit 1 0 1 Reserved Reserved Table 5. UART SPIFI EMC 8-bit EMC 16-bit EMC 32-bit Reserved Reserved SPI [1] LPC1850_30_20_10 1 1 1 1 0 1 Boot mode when OPT BOOT_SRC bits are zero P2_8 LOW LOW LOW LOW HIGH HIGH HIGH HIGH P1_2 LOW LOW HIGH HIGH LOW LOW HIGH HIGH P1_1 LOW HIGH LOW HIGH LOW HIGH LOW HIGH Description Boot from device connected to USART0 using pins P2_0 and P2_1. Boot from Quad SPI flash connected to the SPIFI interface on P3_3 to P3_8[1]. Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. Do not use this option. Do not use this option. Boot from SPI flash connected to the SSP0 interface on P3_3, P3_6, P3_7 and P3_8[1]. Boot mode The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 33 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.9 Memory mapping LPC1850/30/20/10 4 GB reserved 0xE010 0000 ARM private bus reserved SPIFI data 256 MB dynamic external memory DYCS3 256 MB dynamic external memory DYCS2 reserved peripheral bit band alias region reserved reserved reserved reserved AES high-speed GPIO APB peripherals #3 reserved APB peripherals #2 0x2000 0000 0x1F00 0000 0x1E00 0000 0x1D00 0000 0x1C00 0000 16 MB static external memory CS3 16 MB static external memory CS2 16 MB static external memory CS1 16 MB static external memory CS0 reserved APB peripherals #1 reserved APB peripherals #0 reserved 0x4006 0000 clocking/reset peripherals RTC domain peripherals reserved reserved 1 GB 0x4001 2000 AHB peripherals 256 MB dynamic external memory DYCS1 128 MB dynamic external memory DYCS0 0x1040 8000 0x1040 0000 0x1008 A000 32 kB ROM reserved 32 kB + 8 kB local SRAM (LPC1850/30/20/10) reserved 32 kB local SRAM (LPC1850/30) 64 kB local SRAM (LPC1850/30/20/10) 0x1000 0000 reserved 0x2400 0000 32 MB AHB SRAM bit banding 0x2200 0000 reserved 0x2001 0000 16 kB AHB SRAM (LPC1850/30/20) 16 kB AHB SRAM (LPC1850/30/20/10) 16 kB AHB SRAM (LPC1850/30/20) 16 kB AHB SRAM (LPC1850/30/20/10) local SRAM/ external static memory banks 0 GB 256 MB shadow area 0x2000 C000 0x2000 8000 0x2000 4000 0x2000 0000 0x1000 0000 0x0000 0000 002aaf228 0xFFFF FFFF 0xE000 0000 0x8800 0000 0x8000 0000 0x7000 0000 0x6000 0000 0x4400 0000 0x4200 0000 0x4010 2000 0x4010 1000 0x4010 0000 0x400F 2000 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0x4005 0000 0x4004 0000 0x4000 0000 0x3000 0000 0x2800 0000 0x1008 0000 0x1001 8000 0x1001 0000 Fig 4. LPC1850/30/20/10 Memory mapping (overview) LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 34 of 84 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Objective data sheet Rev. 1 -- 3 January 2011 35 of 84 LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. NXP Semiconductors LPC1850/30/20/10 0x400F 0000 0x400E 5000 0x400E 4000 0x400E 3000 0x400E 2000 0x400E 1000 0x400E 0000 0x400D 0000 0x400C 7000 0x400C 6000 0x400C 5000 0x400C 4000 0x400C 3000 0x400C 2000 0x400C 1000 0x400C 0000 0x400B 0000 0x400A 3000 0x400A 2000 0x400A 1000 0x400A 0000 0x4009 0000 0x4008 7000 0x4008 6000 0x4008 5000 0x4008 4000 0x4008 3000 0x4008 2000 0x4008 1000 0x4008 0000 reserved system control timer1 timer0 SSP0 UART1 w/ modem USART0 WWDT 0x0000 0000 002aaf229 reserved ADC1 ADC0 C_CAN DAC I2C1 reserved reserved QEI SSP1 timer3 timer2 USART3 USART2 RI timer APB2 peripherals reserved reserved reserved AES high-speed GPIO APB peripherals #3 reserved APB peripherals #2 reserved I2S0 I2C0 motor control PWM APB1 peripherals reserved APB peripherals #1 reserved APB peripherals #0 reserved clocking/reset peripherals RTC domain peripherals reserved APB0 peripherals 0x4001 2000 AHB peripherals 0x4000 0000 SRAM memories external memory banks peripheral bit band alias region reserved APB3 peripherals 0xFFFF FFFF external memories and ARM private bus 0x6000 0000 0x4400 0000 0x4200 0000 0x4010 2000 0x4010 1000 0x4010 0000 0x400F 2000 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0x4006 0000 0x4005 0000 0x4004 0000 AHB peripherals ethernet reserved LCD USB1 USB0 EMC SD/MMC SPIFI DMA reserved SCT RTC domain peripherals reserved RTC OTP controller event router CREG power mode control backup registers alarm timer 0x4004 7000 0x4004 6000 0x4004 5000 0x4004 4000 0x4004 3000 0x4004 2000 0x4004 1000 0x4004 0000 0x4001 2000 0x4001 0000 0x4000 9000 0x4000 8000 0x4000 7000 0x4000 6000 0x4000 5000 0x4000 4000 0x4000 3000 0x4000 2000 0x4000 1000 0x4000 0000 reserved clocking and reset control peripherals RGU CCU2 CCU1 CGU 0x4006 0000 0x4005 4000 0x4005 3000 0x4005 2000 0x4005 1000 0x4005 0000 32-bit ARM Cortex-M3 microcontroller LPC1850/30/20/10 Fig 5. LPC1850/30/20/10 Memory mapping (peripherals) NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.10 Security features 7.10.1 AES decryption engine The hardware AES engine can decrypt data using the AES algorithm. 7.10.1.1 Features * * * * Decryption of external flash data connected to the quad SPI Flash Interface (SPIFI). Secure storage of decryption keys. Support for CMAC hash calculation to authenticate encrypted data. Data is processed in little endian mode. This means that the first byte read from flash is integrated into the AES codeword as least significant byte. The 16th byte read from flash is the most significant byte of the first AES codeword. * AES engine performance of 1 byte/clock cycle. * DMA transfers supported through the GPDMA. 7.10.2 One-Time Programmable (OTP) memory The OTP provides two 128-bit non-volatile memories to store AES decryption keys or other custom data. 7.11 General Purpose I/O (GPIO) The LPC1850/30/20/10 provides 5 GPIO ports with up to 16 GPIO pins each. Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. All GPIO pins default to inputs with pull-up resistors enabled on reset. 7.11.1 Features * Accelerated GPIO functions: - GPIO registers are located on the AHB so that the fastest possible I/O timing can be achieved. - Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. - All GPIO registers are byte and half-word addressable. - Entire port value can be written in one instruction. * Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. * Direction control of individual bits. * All I/O default to inputs after reset. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 36 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.12 AHB peripherals 7.12.1 State Configurable Timer (SCT) subsystem The SCT allows a wide variety of timing, counting, output modulation, and input capture operations. The inputs and outputs of the SCT are shared with the capture and match inputs/outputs of the 32-bit general purpose counter/timers. The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half: * State variable * Limit, halt, stop, and start conditions * Values of Match/Capture registers, plus reload or capture control values In the two-counter case, the following operational elements are global to the SCT, but the last three can use match conditions from either counter: * * * * * 7.12.1.1 Clock selection Inputs Events Outputs Interrupts Features * * * * * * * * Two 16-bit counters or one 32-bit counter. Counter(s) clocked by bus clock or selected input. Up counter(s) or up-down counter(s). State variable allows sequencing across multiple counter cycles. Event combines input or output condition and/or counter match in a specified state. Events control outputs and interrupts. Selected event(s) can limit, halt, start, or stop a counter. Supports: - up to 8 inputs (one input connected internally) - up to 16 outputs - 16 match/capture registers - 16 events - 32 states 7.12.2 General Purpose DMA (GPDMA) The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 37 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller example, a bidirectional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral for master 1, but only memory for master 0. 7.12.2.1 Features * Eight DMA channels. Each channel can support an unidirectional transfer. * 16 DMA request lines. * Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. * Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. * Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. * Hardware DMA channel priority. * AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. * Two AHB bus masters for transferring data. These interfaces transfer data when a DMA request goes active. Master 1 can access memories and peripherals, master 0 can access memories only. * 32-bit AHB master bus width. * Incrementing or non-incrementing addressing for source and destination. * Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. * Internal four-word FIFO per channel. * Supports 8, 16, and 32-bit wide transactions. * Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. * An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. * Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.12.3 SPI Flash Interface (SPIFI) The SPI Flash Interface (allows low-cost serial flash memories to be connected to the ARM Cortex-M3 processor with little performance penalty compared to parallel flash devices with higher pin count. After a few commands configure the interface at startup, the entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. Erasure and programming are handled by simple sequences of commands. Many serial flash devices use a half-duplex command-driven SPI protocol for device setup and initialization and then move to a half-duplex, command-driven 4-bit protocol for normal operation. Different serial flash vendors and devices accept or require different LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 38 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller commands and command formats. SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices. 7.12.3.1 Features * * * * * Interfaces to serial flash memory in the main memory map. Supports classic and 4-bit bidirectional serial protocols. Half-duplex protocol compatible with various vendors and devices. Data rates of up to 40 MB per second total. Supports DMA access. 7.12.4 SD/MMC card interface The SD/MMC card interface supports the following modes to control: * * * * Secure Digital memory (SD version 3.0) Secure Digital I/O (SDIO version 2.0) Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1) Multimedia Cards (MMC version 4.4) 7.12.5 External Memory Controller (EMC) The LPC1850/30/20/10 EMC is a Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. 7.12.5.1 Features * Dynamic memory interface support including single data rate SDRAM. * Asynchronous static memory device support including RAM, ROM, and NOR flash, with or without asynchronous page mode. * Low transaction latency. * Read and write buffers to reduce latency and to improve performance. * 8/16/32 data and 24 address lines wide static memory support. On parts LPC1820/10 only 8/16 data lines are available. * 16 bit and 32 bit wide chip select SDRAM memory support. * Static memory features include: - Asynchronous page mode read - Programmable Wait States - Bus turnaround delay - Output enable and write enable delays - Extended wait * Four chip selects for synchronous memory and four chip selects for static memory devices. * Power-saving modes dynamically control CKE and CLKOUT to SDRAMs. * Dynamic memory self-refresh mode controlled by software. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 39 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller * Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. * Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.12.6 High-speed USB Host/Device/OTG interface (USB0) Remark: USB0 is not available on the LPC1810 (see Table 2). The USB OTG module allows the part to connect directly to a USB host such as a PC (in device mode) or to a USB device in host mode. 7.12.6.1 Features * * * * * * * Complies with Universal Serial Bus specification 2.0. Complies with USB On-The-Go supplement. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals. Supports all full-speed USB-compliant peripherals. Supports software Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG peripherals. * Contains UTMI+ compliant transceiver (PHY). * Supports interrupts. * This module has its own, integrated DMA engine. 7.12.7 High-speed USB Host/Device interface with ULPI (USB1) Remark: USB1 is not available on the LPC1820/10 (see Table 2). The USB1 interface can operate as a full-speed USB host/device interface or can connect to an external ULPI PHY for High-speed operation. 7.12.7.1 Features * * * * Complies with Universal Serial Bus specification 2.0. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals if connected to external ULPI PHY. * Supports all full-speed USB-compliant peripherals. * Supports interrupts. * This module has its own, integrated DMA engine. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 40 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.12.8 LCD controller The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024 x 768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.12.8.1 Features * * * * AHB master interface to access frame buffer. Setup and control via a separate AHB slave interface. Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. * Supports single and dual-panel color STN displays. * Supports Thin Film Transistor (TFT) color displays. * Programmable display resolution including, but not limited to: 320 x 200, 320 x 240, 640 x 200, 640 x 240, 640 x 480, 800 x 600, and 1024 x 768. Hardware cursor support for single-panel displays. 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized for color STN and TFT. 24 bpp true-color non-palettized for color TFT. Programmable timing for different display panels. 256 entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. LCD panel clock may be generated from the peripheral clock, or from a clock input pin. * * * * * * * * * * * * 7.12.9 Ethernet Remark: Ethernet is not available on the LPC1820/10 (see Table 2). 7.12.9.1 Features * 10/100 Mbit/s * TCP/IP hardware checksum LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 41 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller * * * * IP checksum DMA support Power management remote wake-up frame and magic packet detection Supports both full-duplex and half-duplex operation - Supports CSMA/CD Protocol for half-duplex operation. - Supports IEEE 802.3x flow control for full-duplex operation. - Optional forwarding of received pause control frames to the user application in full-duplex operation. - Back-pressure support for half-duplex operation. - Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex operation. 7.13 Digital serial peripherals 7.13.1 UART1 The LPC1850/30/20/10 contain one UART with standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.13.1.1 Features * * * * * Maximum UART data bit rate of * Auto baud capabilities and FIFO control mechanism that enables software flow * Equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). * Support for RS-485/9-bit/EIA-485 mode (UART1). * DMA support. 7.13.2 USART0/2/3 The LPC1850/30/20/10 contain three USARTs. In addition to standard transmit and receive data lines, the USARTs support a synchronous mode. The USARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 42 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.13.2.1 Features * * * * * Maximum UART data bit rate of * Auto baud capabilities and FIFO control mechanism that enables software flow * * * * * Support for RS-485/9-bit/EIA-485 mode. USART3 includes an IrDA mode to support infrared communication. All USARTs have DMA support. Support for synchronous mode. Smart card mode conforming to ISO7816 specification 7.13.3 SSP0/1 serial I/O controllers The LPC1850/30/20/10 contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.13.3.1 Features * Maximum SSP speed of Semiconductor Microwire buses * * * * * Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame DMA transfers supported by GPDMA 7.13.4 I2C0/1-bus interfaces The LPC1850/30/20/10 each contain two I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 43 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.13.4.1 Features * I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also supports Fast mode plus with bit rates up to 1 Mbit/s. * * * * * * I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus. * Serial clock synchronization allows devices with different bit rates to communicate via * Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. * The I2C-bus can be used for test and diagnostic purposes. * All I2C-bus controllers support multiple address recognition and a bus monitor mode. 7.13.5 I2S interface The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.13.5.1 Features * The interface has separate input/output channels each of which can operate in master or slave mode. * Capable of handling 8-bit, 16-bit, and 32-bit word sizes. * Mono and stereo audio data supported. * The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48, 96) kHz. * Support for an audio master clock. * Configurable word select period in master mode (separately for I2S-bus input and output). * Two 8-word FIFO data buffers are provided, one for transmit and one for receive. * Generates interrupt requests when buffer levels cross a programmable boundary. * Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. * Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus output. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 44 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.13.6 C_CAN Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of security. 7.13.6.1 Features * * * * * * * Conforms to protocol version 2.0 parts A and B. Supports bit rate of up to 1 Mbit/s. Supports 32 Message Objects. Each Message Object has its own identifier mask. Provides programmable FIFO mode (concatenation of Message Objects). Provides maskable interrupts. Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN applications. * Provides programmable loop-back mode for self-test operation. 7.14 Counter/timers and motor control 7.14.1 General purpose 32-bit timers/external event counters The LPC1850/30/20/10 include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.14.1.1 Features * A 32-bit timer/counter with a programmable 32-bit prescaler. * Counter or timer operation. * Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. * Four 32-bit match registers that allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. * Up to four external outputs corresponding to match registers, with the following capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 45 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller * Up to two match registers can be used to generate timed DMA requests. 7.14.2 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. 7.14.3 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 7.14.3.1 Features * * * * * * * * * * Tracks encoder position. Increments/decrements depending on direction. Programmable for 2x or 4x position counting. Velocity capture using built-in timer. Velocity compare function with "less than" interrupt. Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. * Digital filter with programmable delays for encoder input signals. * Can accept decoded signal inputs (clk and direction). 7.14.4 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 7.14.4.1 Features * 32-bit counter. Counter can be free-running or be reset by a generated interrupt. * 32-bit compare value. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 46 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller * 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 7.14.5 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.14.5.1 Features * Internally resets chip if not periodically reloaded during the programmable time-out period. * Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. * Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. * * * * Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) x 256 x 4) to (Tcy(WDCLK) x 224 x 4) in multiples of Tcy(WDCLK) x 4. * The Watchdog Clock (WDCLK) uses the IRC as the clock source. 7.15 Analog peripherals 7.15.1 Analog-to-Digital Converter (ADC0/1) 7.15.1.1 Features * * * * * * * 10-bit successive approximation analog to digital converter. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 to 3 V. Sampling frequency up to 400 kSamples/s. Burst conversion mode for single or multiple inputs. Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer outputs 8 or 15, or the PWM output MCOA2. * Individual result registers for each A/D channel to reduce interrupt overhead. * DMA support. 7.15.2 Digital-to-Analog Converter (DAC) 7.15.2.1 Features * 10-bit resolution LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 47 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller * * * * * Integral Non-Linearity Differential Non-Linearity Monotonic by design (resistor string architecture) Controllable conversion speed Low power consumption 7.16 Peripherals in the RTC power domain 7.16.1 RTC The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses very little power when its registers are not being accessed by the CPU, especially reduced power modes. The RTC is clocked by a separate 32 kHz oscillator that produces a 1 Hz internal time reference and is powered by its own power supply pin, VBAT. 7.16.1.1 Features * Measures the passage of time to maintain a calendar and clock. Provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. * Ultra-low power design to support battery powered systems. Less than for battery operation. Uses power from the CPU power supply when it is present. * * * * * Dedicated battery power supply pin. RTC power supply is isolated from the rest of the chip. Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution. Periodic interrupts can be generated from increments of any field of the time registers. Alarm interrupt can be generated for a specific date/time. 7.16.2 Alarm timer The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled. The alarm timer is part of the RTC power domain and can be battery powered. 7.17 System control 7.17.1 Configuration registers (CREG) The following settings are controlled in the configuration register block: * * * * * * * LPC1850_30_20_10 BOD trip settings Oscillator output DMA-to-peripheral muxing Ethernet mode Memory mapping Timer/USART inputs Enabling the USB controllers All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 48 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller In addition, the CREG block contains the part identification and part configuration information. 7.17.2 System Control Unit (SCU) The system control unit determines the function and electrical mode of the digital pins. By default function 0 is selected for all pins with pull-up enabled. Analog I/Os for the ADCs and the DAC as well as most USB pins are on separate pads and are not controlled through the SCU. 7.17.3 Clock Generation Unit (CGU) The Clock Generator Unit (CGU) generates several base clocks. The base clocks may be unrelated in frequency and phase and can have different clock sources within the CGU. One CGU base clock is routed to the CLKOUT pins. Derived from each base clock may be multiple branch clocks. The branch clocks offer very flexible control for power-management purposes. All branch clocks are outputs of one of two Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. 7.17.4 Internal RC oscillator (IRC) The IRC is used as the clock source for the WWDT and/or as the clock that drives the PLLs and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC1850/30/20/10 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.17.5 PLL0 (for USB0) PLL0 is a dedicated PLL for the USB0 High-speed controller. PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz. 7.17.6 System PLL1 The PLL1 accepts an input clock frequency from an external oscillator in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.17.7 Reset Generation Unit (RGU) The RGU allows generation of independent reset signals for individual blocks and peripherals. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 49 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.17.8 Power control The LPC1850/30/20/10 support four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. The LPC1850/30/20/10 can wake up from Deep-sleep, Power-down, and Deep power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery powered blocks in the RTC power domain. 7.18 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 50 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(REG)(3V3) VDD(IO) VDDA(3V3) VBAT Vprog(pf) VIA VI Parameter regulator supply voltage (3.3 V) I/O supply voltage analog supply voltage (3.3 V) battery supply voltage polyfuse programming voltage analog input voltage input voltage on ADC pins only valid when the VDD(IO) supply voltage is present per supply pin per ground pin -(0.5VDD(IO)) < VI < (1.5VDD(IO)); Tj < 125 C Tstg Ptot(pack) storage temperature total power dissipation (per package) based on package heat transfer, not device power consumption human body model; all pins [6] [5] [3] Conditions on pin VDD_REG on pin VDDIO on pin VDDA for the RTC on pin VPP Min 2.2[2] 2.2 2.0 2.2 2.7 0 2.0 Max 3.6 3.6 3.6 3.6 3.6 VDDA(3V3) 3.6 Unit V V V V V V V IDD ISS Ilatch supply current ground current I/O latch-up current [4] [4] - mA mA mA C W VESD electrostatic discharge voltage V [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] [3] [4] [5] [6] 2.0 V if VBAT 2.2 V. Including voltage on outputs in 3-state mode; at 2.0 V the speed will be reduced. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 51 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb + ( P D x R th ( j - a ) ) (1) * Tamb = ambient temperature (C), * Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) * PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 7. Thermal characteristics VDD = 2.2 V to 3.6 V; Tamb = -40 C to +85 C unless otherwise specified; Symbol Tj(max) Parameter maximum junction temperature Conditions Min Typ Max LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 52 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 10. Static characteristics Table 8. Static characteristics Tamb = -40 C to +85 C, unless otherwise specified. Symbol Supply pins VDD(IO) VDD(REG)(3V3) VDDA(3V3) VBAT IDD(REG)(3V3) I/O supply voltage regulator supply voltage (3.3 V) analog supply voltage (3.3 V) battery supply voltage regulator supply current active mode; code (3.3 V) while(1){} executed from [5] [6] [3] [2] Parameter Conditions Min 2.2 2.2 2.0 2.2 Typ[1] - Max 3.6 3.6 3.6 3.6 Unit V V V V - - mA mA mA mA A A nA [3] [3] [3] [3][4] [3][4] [3] - - nA nA nA nA nA nA nA nA [7] [7] [7] [8] [8] [8] - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 53 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 8. Static characteristics ...continued Tamb = -40 C to +85 C, unless otherwise specified. Symbol Digital pins IIL IIH LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current IOH = -4 mA IOL = 4 mA VOH = VDD(IO) - 0.4 V VOL = 0.4 V [12] Parameter Conditions Min - Typ[1] - Max Unit A A VI = VDD(IO); on-chip pull-down resistor disabled VO = 0 V; VO = VDD(IO); on-chip pull-up/down resistors disabled pin configured to provide a digital function output active [9][10] [11] IOZ - - A VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS Ipd Ipu V V V V V V V mA mA mA mA A A A V V V V A A HIGH-level short-circuit VOH = 0 V output current LOW-level short-circuit output current pull-down current pull-up current VOL = VDD(IO) VI = 3.6 V VI = 0 V VDD(IO) < VI < 3.6 V [12] Open-drain I2C0-bus pins VIH VIL Vhys VOL ILI HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS = [13] - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 54 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 8. Static characteristics ...continued Tamb = -40 C to +85 C, unless otherwise specified. Symbol Oscillator pins Vi(XTAL1) Vo(XTAL2) USB pins VIC common-mode input voltage high-speed mode full-speed/low-speed mode chirp mode Vi(dif) [1] [2] [3] [4] [5] [6] [7] [8] [9] Parameter input voltage on pin XTAL1 output voltage on pin XTAL2 Conditions Min -0.5 -0.5 Typ[1] - Max 1.2 1.2 Unit V V mV mV mV mV differential input voltage Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. The RTC typically fails when VVBAT drops below 1.6 V. VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements. Conditions [10] VDD(3V3) supply voltages must be present. [11] 3-state outputs go into 3-state mode in Deep power-down mode. [12] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [13] To VSS. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 55 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 10.1 Electrical pin characteristics X X (X) X 001aab173 X X (X) X 001aab173 X X X X X X X X (X) X X X X X X X X X (X) X X X X X Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins. Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins. Fig 6. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH Fig 7. Typical LOW-level output current IOL versus LOW-level output voltage VOL X X (X) X 001aab173 X X (X) X 001aab173 X X X X X X X X (X) X X X X X X X X X (X) X X X X X Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins. Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins. Fig 8. Typical pull-up current Ipu versus input voltage VI Fig 9. Typical pull-down current Ipd versus input voltage VI LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 56 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 10.2 Power consumption X X (X) X 001aab173 X X (X) X 001aab173 X X X X X X X X (X) X X X X X X X X X (X) X X X X X Conditions: Tamb = 25 C; VDD(REEG)(3V3) = 3.3 V; Conditions: Tamb = 25 C; VDD(REEG)(3V3) = 3.3 V; Fig 10. Typical supply current versus regulator supply voltage VDD(REEG)(3V3) in active mode Fig 11. Typical supply current versus temperature in active mode X X (X) X 001aab173 X X (X) X 001aab173 X X X X X X X X (X) X X X X X X X X X (X) X X X X X Conditions: Tamb = 25 C; Conditions: Tamb = 25 C; V; Fig 12. Typical supply current versus temperature in Sleep mode Fig 13. Typical supply current versus temperature in Deep-sleep mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 57 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller X X (X) X 001aab173 X X (X) X 001aab173 X X X X X X X X (X) X X X X X X X X X (X) X X X X X Conditions: Tamb = 25 C; Conditions: Tamb = 25 C; V; Fig 14. Typical supply current versus temperature in Power-down mode Fig 15. Typical supply current versus temperature in Deep power-down mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 58 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 9. Power consumption for individual peripherals Tamb = 25 C; VDD(REEG)(3V3) = 3.3 V. Peripheral IRC ADC DAC I2C0 I2C1 I2S SSP0 SSP1 USART0 UART1 USART2 USART3 USB0 USB1 Ethernet [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Conditions Typical IDD[1] LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 59 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 11. Dynamic characteristics 11.1 External clock Table 10. Dynamic characteristic: external clock Tamb = -40 C to +85 C; VDD(IO) over specified ranges.[1] Symbol Parameter fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL [1] [2] Conditions Min 1 40 Tcy(clk) x Typ[2] - Max 25 1000 Unit MHz ns ns ns ns ns oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. tCHCL tCLCX Tcy(clk) tCHCX tCLCH 002aaa907 Fig 16. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 -- 3 January 2011 60 of 84 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 11.2 IRC and RTC oscillators Table 11. Dynamic characteristic: IRC and RTC oscillators Tamb = -40 C to +85 C; [1] [2] Parameter internal RC oscillator frequency RTC input frequency Conditions - Min Typ[2] 12.00 32.768 Max |